A 24 bit accumulator is the basis for waveform generation. FREQ is added to the lower 16 bits of the accumulator each cycle. The accumulator is set to zero when TEST is set, and starts counting when TEST is cleared.
Waveforms are generated as follows:
- No waveform: When no waveform is selected, the DAC input is floating.
- Triangle: The upper 12 bits of the accumulator are used. The MSB is used to create the falling edge of the triangle by inverting the lower 11 bits. The MSB is thrown away and the lower 11 bits are left-shifted (half the resolution, full amplitude). Ring modulation substitutes the MSB with MSB EOR NOT sync_source MSB.
- Sawtooth: The output is identical to the upper 12 bits of the accumulator.
- Pulse: The upper 12 bits of the accumulator are used. These bits are compared to the pulse width register by a 12 bit digital comparator; output is either all one or all zero bits. The pulse setting is delayed one cycle after the compare. The test bit, when set to one, holds the pulse waveform output at 0xfff regardless of the pulse width setting.
- Noise: The noise output is taken from intermediate bits of a 23-bit shift register which is clocked by bit 19 of the accumulator. The shift is delayed 2 cycles after bit 19 is set high.
Operation: Calculate EOR result, shift register, set bit 0 = result.
reset -------------------------------------------
| | |
test--OR-->EOR<-- |
| | |
2 2 2 1 1 1 1 1 1 1 1 1 1 |
Register bits: 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---
| | | | | | | |
Waveform bits: 1 1 9 8 7 6 5 4
1 0
The low 4 waveform bits are zero (grounded).
