25 #include "resid-config.h"
28 #include "filter8580new.h"
44 void set_chip_model(chip_model model);
45 void set_voice_mask(reg4 mask);
46 void enable_filter(
bool enable);
47 void adjust_filter_bias(
double dac_bias);
48 void enable_external_filter(
bool enable);
49 bool set_sampling_parameters(
double clock_freq, sampling_method method,
50 double sample_freq,
double pass_freq = -1,
51 double filter_scale = 0.97);
52 void adjust_sampling_frequency(
double sample_freq);
55 void clock(cycle_count delta_t);
56 int clock(cycle_count& delta_t,
short* buf,
int n,
int interleave = 1);
60 reg8 read(reg8 offset);
61 void write(reg8 offset, reg8 value);
69 char sid_register[0x20];
72 cycle_count bus_value_ttl;
73 cycle_count write_pipeline;
78 reg24 shift_register[3];
79 cycle_count shift_register_reset[3];
80 cycle_count shift_pipeline[3];
81 reg16 pulse_output[3];
82 cycle_count floating_output_ttl[3];
84 reg16 rate_counter[3];
85 reg16 rate_counter_period[3];
86 reg16 exponential_counter[3];
87 reg16 exponential_counter_period[3];
88 reg8 envelope_counter[3];
89 EnvelopeGenerator::State envelope_state[3];
91 cycle_count envelope_pipeline[3];
95 void write_state(
const State& state);
98 void input(
short sample);
104 static double I0(
double x);
105 int clock_fast(cycle_count& delta_t,
short* buf,
int n,
int interleave);
106 int clock_interpolate(cycle_count& delta_t,
short* buf,
int n,
int interleave);
107 int clock_resample(cycle_count& delta_t,
short* buf,
int n,
int interleave);
108 int clock_resample_fastmem(cycle_count& delta_t,
short* buf,
int n,
int interleave);
111 chip_model sid_model;
119 cycle_count bus_value_ttl;
122 cycle_count databus_ttl;
125 cycle_count write_pipeline;
128 double clock_frequency;
140 FIR_RES_FASTMEM = 51473,
144 RINGMASK = RINGSIZE - 1,
152 sampling_method sampling;
153 cycle_count cycles_per_sample;
154 cycle_count sample_offset;
156 short sample_prev, sample_now;
160 double fir_f_cycles_per_sample;
161 double fir_filter_scale;
177 #if RESID_INLINING || defined(RESID_SID_CC)
185 return extfilt.output();
198 for (i = 0; i < 3; i++) {
199 voice[i].envelope.clock();
203 for (i = 0; i < 3; i++) {
204 voice[i].wave.clock();
208 for (i = 0; i < 3; i++) {
209 voice[i].wave.synchronize();
213 for (i = 0; i < 3; i++) {
214 voice[i].wave.set_waveform_output();
218 filter.clock(voice[0].output(), voice[1].output(), voice[2].output());
221 extfilt.clock(filter.output());
224 if (unlikely(write_pipeline)) {
229 if (unlikely(!--bus_value_ttl)) {
234 #endif // RESID_INLINING || defined(RESID_SID_CC)
238 #endif // not RESID_SID_H